1. Technical Field
The present invention relates in general to digital and analog integrated circuits, and in particular to digital and analog oscillator circuits. More particularly, the present invention relates to phase detectors utilized in integrated circuits. Still more particularly, the present invention relates to phase locked loop circuits. In addition, the present invention relates to methods and systems for detecting phase differences in clock signals utilized in phase locked loop circuits.
2. Description of the Related Art
It is often desirable to detect phase differences between two signals generated by integrated circuits. A phase difference, graphically represented by the symbol, xe2x80x9cxc3x8xe2x80x9d, is the difference in phase between two periodically varying quantities of the same frequency. The phase difference may be expressed as an angle (i.e, the xe2x80x9cphase anglexe2x80x9d) or as function of time. The phase itself is simply the stage of a periodically recurring quantity, and is a fraction of the period that has elapsed with respect to a fixed datum point.
An example of a type of integrated circuit in which it is desirable to detect such phase differences is a phase-locked loop (PLL) circuit. A phase-locked loop circuit is a type of circuit that utilizes feedback to maintain an output signal in specific relationship with a reference signal. Phase-locked loop circuits are utilized in many areas of electronics to control the frequency and/or phase of a signal. These applications include frequency synthesizers, analog and digital modulators and demodulators, and clock recovery circuits.
A phase-locked loop circuit typically includes a phase detector which compares two signals. A problem that every circuit designer must face, however, is the difficulty in amplifying the phase difference for efficient and relatively easy detection. For example, when two signals whose phases are relatively synchronized, but remain 20 picoseconds apart, it is very difficult for the phase detector utilized by the phase-locked loop circuit to exactly determine whether one signal is running ahead of or behind the other signal.
The phase detector, a circuit which produces an output proportional to the phase difference between two inputs, detects a positive difference or a negative difference for the same phase, often resulting in misleading determinations and inaccurate data. Ideally, to avoid misleading determinations and inaccurate data, a delay should be amplified first. If the phase difference is expanded from 20 picoseconds to 100 picoseconds, the phase detector may readily detect which signal is running ahead of or behind the other.
Most prior art designs have been chiefly based on analog techniques. A multiplier is a device that has two or more inputs and that produces an output of magnitude equal to the product of the magnitudes of the input signals. In analog-signal processing, the need often arises for a circuit which takes two analog inputs and produces an output proportional to their product. Such circuits are termed analog multipliers. Utilizing such analog multipliers and other similar analog-based techniques, results in a xe2x80x9cdead zonexe2x80x9d in the phase difference. As the phase difference becomes increasingly narrow, the detection capability about the phase difference approaches zero (i.e., the dead zone) and becomes very poor.
From the foregoing, it can be appreciated that a need exists for a circuit technique which would limit or eliminate altogether a phase difference that approaches a zero value in phase-locked loop circuits, particularly those integrated circuits which are based on asynchronous designs. In view of the fact that detecting phase differences in phase-locked loop circuits is often a particularly difficult task, any improvements in the ability to detect phases in such circuits would be a welcome advance to the integrated circuit arts. Such an advance would improve both the efficiency and speed of circuits which take advantage of phase-locked loop circuits.
It is therefore one object of the present invention to provide improved integrated circuits.
It is therefore another object of the present invention to provide improved digital and analog oscillator circuits.
It is yet another object of the present invention to provide improved phase detectors utilized in digital and analog oscillator circuits.
It is yet another object of the present invention to provide an improved phase locked loop circuit utilized in digital and analog oscillator circuits.
It is still another object of the present invention to provide an improved method and system for detecting phase differences evidenced in phase locked loop circuits.
The above and other objects are achieved as is now described. An apparatus and method in an integrated circuit for detecting phase differences between clock signals originating from an oscillator circuit. The oscillator circuit is formed on a substrate, such that the oscillator circuit is coupled to coincidence elements responsive to clock signals originating from the oscillator circuit. In addition, a coincidence circuit is provided that includes the coincidence elements, such that the coincidence circuit provides output signals only in response to a change in all clock signals originating from the oscillator circuit. The apparatus includes a delay circuit responsive to the output signals, such that the delay circuit stretches delays between the clock signals. A phase detector is coupled to the delay circuit, such that the phase detector is responsible for detecting phase differences between the clock signals by identifying the delays. The phase detector circuit is further coupled to a buffer circuit which compensates phase differences by delaying a faster clock signal until an associated clock signal matches the phase of the faster clock signal.